The present invention relates to a data transmission system for accomplishing differential transmission of each of a plurality of data bits.
Against the background of an enormous amount of dynamic image data to be processed, high-speed data transmission between a plurality of semiconductor integrated circuits mounted on a printed wiring board has been in increasing demand. To satisfy the demand, a Rambus standard and a SyncLink standard have been known in the field of DRAM (dynamic random access memory) development as standards for clock-synchronized high-speed I/O interfaces. The former standard has been developed by Rambus, Inc. and adopts an open-drain interface. The latter standard has been proposed by JEDEC (Joint Electron Device Engineering Council) and adopts a low-amplitude interface termed a SSTL (stub series terminated transceiver logic) interface.
Each of the conventional I/O interface standards mentioned above has been devised to transmit one data bit over a single data line. Such a single-ended transmission scheme has the drawback of susceptibility to external noise.
There has conventionally been known differential data transmission which is excellent in common-mode noise rejecting performance. The differential data transmission accomplishes the transmission of one data bit by using a pair of data lines. However, if each of a plurality of data bits is to be differentially transmitted between semiconductor integrated circuits on a printed wiring board, the number of lines required is doubled compared with the number of wires used in the foregoing single-ended transmission scheme. As a result, the problems occur that the wiring region occupies a larger area of the surface of the printed wiring board and that a package for the semiconductor integrated circuit should have an increased number of pins.